func (h handle) deviceGetMaxPcieLinkWidth() (*uint, error) {
var width C.uint
r := C.nvmlDeviceGetMaxPcieLinkWidth(h.dev, &width)
if r == C.NVML_ERROR_NOT_SUPPORTED {
return nil, nil
}
return uintPtr(width), errorString(r)
}
func NewDevice(idx uint) (device *Device, err error) {
var (
dev C.nvmlDevice_t
model [szModel]C.char
uuid [szUUID]C.char
pci C.nvmlPciInfo_t
minor C.uint
bar1 C.nvmlBAR1Memory_t
power C.uint
clock [2]C.uint
pciel [2]C.uint
mask cpuMask
)
defer func() {
if r := recover(); r != nil {
err = r.(error)
}
}()
assert(C.nvmlDeviceGetHandleByIndex(C.uint(idx), &dev))
assert(C.nvmlDeviceGetName(dev, &model[0], szModel))
assert(C.nvmlDeviceGetUUID(dev, &uuid[0], szUUID))
assert(C.nvmlDeviceGetPciInfo(dev, &pci))
assert(C.nvmlDeviceGetMinorNumber(dev, &minor))
assert(C.nvmlDeviceGetBAR1MemoryInfo(dev, &bar1))
assert(C.nvmlDeviceGetPowerManagementLimit(dev, &power))
assert(C.nvmlDeviceGetMaxClockInfo(dev, C.NVML_CLOCK_SM, &clock[0]))
assert(C.nvmlDeviceGetMaxClockInfo(dev, C.NVML_CLOCK_MEM, &clock[1]))
assert(C.nvmlDeviceGetMaxPcieLinkGeneration(dev, &pciel[0]))
assert(C.nvmlDeviceGetMaxPcieLinkWidth(dev, &pciel[1]))
assert(C.nvmlDeviceGetCpuAffinity(dev, C.uint(len(mask)), (*C.ulong)(&mask[0])))
cpu, err := mask.cpuNode()
if err != nil {
return nil, err
}
device = &Device{
handle: dev,
Model: C.GoString(&model[0]),
UUID: C.GoString(&uuid[0]),
Path: fmt.Sprintf("/dev/nvidia%d", uint(minor)),
Power: uint(power / 1000),
CPUAffinity: cpu,
PCI: PCIInfo{
BusID: C.GoString(&pci.busId[0]),
BAR1: uint64(bar1.bar1Total / (1024 * 1024)),
Bandwidth: pcieGenToBandwidth[int(pciel[0])] * uint(pciel[1]) / 1000,
},
Clocks: ClockInfo{
Core: uint(clock[0]),
Memory: uint(clock[1]),
},
}
return
}