Example #1
0
File: x86.go Project: tsavola/wag
// OpStoreStackReg must not allocate registers.
func (mach X86) OpStoreStackReg(code gen.OpCoder, t types.T, offset int32, reg regs.R) {
	switch t.Category() {
	case types.Int:
		Mov.opToStack(code, t, reg, offset)

	case types.Float:
		MovsSSE.opToStack(code, t, reg, offset)

	default:
		panic(t)
	}
}
Example #2
0
File: insn.go Project: tsavola/wag
func (i movImmInsn) op(code gen.OpCoder, t types.T, reg regs.R, value int64) {
	switch {
	case value >= -0x80000000 && value < 0x80000000:
		i.imm32.opImm(code, t, reg, int32(value))

	case t.Size() == types.Size64 && value >= 0 && value < 0x100000000:
		i.imm.op(code, types.I32, reg, imm{uint32(value)})

	default:
		i.imm.op(code, t, reg, imm{value})
	}
}
Example #3
0
File: float.go Project: tsavola/wag
func (p *floatSizePrefix) writeTo(code gen.OpCoder, t types.T, ro, index, rmOrBase byte) {
	switch t.Size() {
	case types.Size32:
		code.Write(p.size32)

	case types.Size64:
		code.Write(p.size64)

	default:
		panic(t)
	}

	writeRexTo(code, 0, ro, index, rmOrBase)
}
Example #4
0
File: x86.go Project: tsavola/wag
// OpGetGlobal must not update CPU's condition flags.
func (mach X86) OpGetGlobal(code gen.RegCoder, t types.T, offset int32) values.Operand {
	reg, ok := code.TryAllocReg(t)
	if !ok {
		reg = regResult
	}

	if t.Category() == types.Int {
		Mov.opFromIndirect(code, t, reg, 0, NoIndex, regMemoryBase, offset)
	} else {
		MovSSE.opFromIndirect(code, t, reg, 0, NoIndex, regMemoryBase, offset)
	}

	return values.TempRegOperand(t, reg, true)
}
Example #5
0
File: insn.go Project: tsavola/wag
func writeRexSizeTo(code gen.OpCoder, t types.T, ro, index, rmOrBase byte) {
	var rex byte

	switch t.Size() {
	case types.Size32:

	case types.Size64:
		rex |= rexW

	default:
		panic(t)
	}

	writeRexTo(code, rex, ro, index, rmOrBase)
}
Example #6
0
File: x86.go Project: tsavola/wag
// OpMoveReg must not allocate registers.
func (mach X86) OpMoveReg(code gen.Coder, t types.T, targetReg, sourceReg regs.R) {
	if targetReg == sourceReg {
		panic("target and source registers are the same")
	}

	switch t.Category() {
	case types.Int:
		Mov.opFromReg(code, t, targetReg, sourceReg)

	case types.Float:
		MovsSSE.opFromReg(code, t, targetReg, sourceReg)

	default:
		panic(t)
	}
}
Example #7
0
func TypeRegCategory(t types.T) RegCategory {
	return RegCategory(t.Category() - 1)
}