func archPPC64() *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
// Note that there is no list of names as there is for x86.
for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := ppc64.REG_F0; i <= ppc64.REG_F31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ {
register[obj.Rconv(i)] = int16(i)
}
register["CR"] = ppc64.REG_CR
register["XER"] = ppc64.REG_XER
register["LR"] = ppc64.REG_LR
register["CTR"] = ppc64.REG_CTR
register["FPSCR"] = ppc64.REG_FPSCR
register["MSR"] = ppc64.REG_MSR
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
// Avoid unintentionally clobbering g using R30.
delete(register, "R30")
register["g"] = ppc64.REG_R30
registerPrefix := map[string]bool{
"CR": true,
"F": true,
"R": true,
"SPR": true,
}
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range ppc64.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABasePPC64
}
}
// Annoying aliases.
instructions["BR"] = ppc64.ABR
instructions["BL"] = ppc64.ABL
return &Arch{
LinkArch: &ppc64.Linkppc64,
Instructions: instructions,
Register: register,
RegisterPrefix: registerPrefix,
RegisterNumber: ppc64RegisterNumber,
IsJump: jumpPPC64,
}
}
func archMips64() *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
// Note that there is no list of names as there is for x86.
for i := mips.REG_R0; i <= mips.REG_R31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := mips.REG_F0; i <= mips.REG_F31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := mips.REG_M0; i <= mips.REG_M31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
register[obj.Rconv(i)] = int16(i)
}
register["HI"] = mips.REG_HI
register["LO"] = mips.REG_LO
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
// Avoid unintentionally clobbering g using R30.
delete(register, "R30")
register["g"] = mips.REG_R30
// Avoid unintentionally clobbering RSB using R28.
delete(register, "R28")
register["RSB"] = mips.REG_R28
registerPrefix := map[string]bool{
"F": true,
"FCR": true,
"M": true,
"R": true,
}
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range mips.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABaseMIPS64
}
}
// Annoying alias.
instructions["JAL"] = mips.AJAL
return &Arch{
LinkArch: &mips.Linkmips64,
Instructions: instructions,
Register: register,
RegisterPrefix: registerPrefix,
RegisterNumber: mipsRegisterNumber,
IsJump: jumpMIPS64,
}
}
func archS390x() *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
// Note that there is no list of names as there is for x86.
for i := s390x.REG_R0; i <= s390x.REG_R15; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := s390x.REG_F0; i <= s390x.REG_F15; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := s390x.REG_V0; i <= s390x.REG_V31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := s390x.REG_AR0; i <= s390x.REG_AR15; i++ {
register[obj.Rconv(i)] = int16(i)
}
register["LR"] = s390x.REG_LR
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
// Avoid unintentionally clobbering g using R13.
delete(register, "R13")
register["g"] = s390x.REG_R13
registerPrefix := map[string]bool{
"AR": true,
"F": true,
"R": true,
}
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range s390x.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABaseS390X
}
}
// Annoying aliases.
instructions["BR"] = s390x.ABR
instructions["BL"] = s390x.ABL
return &Arch{
LinkArch: &s390x.Links390x,
Instructions: instructions,
Register: register,
RegisterPrefix: registerPrefix,
RegisterNumber: s390xRegisterNumber,
IsJump: jumpS390x,
}
}
func archArm() *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
// Note that there is no list of names as there is for x86.
for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
register[obj.Rconv(i)] = int16(i)
}
// Avoid unintentionally clobbering g using R10.
delete(register, "R10")
register["g"] = arm.REG_R10
for i := 0; i < 16; i++ {
register[fmt.Sprintf("C%d", i)] = int16(i)
}
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
register["SP"] = RSP
registerPrefix := map[string]bool{
"F": true,
"R": true,
}
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range arm.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABaseARM
}
}
// Annoying aliases.
instructions["B"] = obj.AJMP
instructions["BL"] = obj.ACALL
// MCR differs from MRC by the way fields of the word are encoded.
// (Details in arm.go). Here we add the instruction so parse will find
// it, but give it an opcode number known only to us.
instructions["MCR"] = aMCR
return &Arch{
LinkArch: &arm.Linkarm,
Instructions: instructions,
Register: register,
RegisterPrefix: registerPrefix,
RegisterNumber: armRegisterNumber,
IsJump: jumpArm,
}
}
func initproginfo() {
var addvariant = []int{V_CC, V_V, V_CC | V_V}
// Perform one-time expansion of instructions in progtable to
// their CC, V, and VCC variants
for i := range progtable {
as := obj.As(i)
if progtable[as].Flags == 0 {
continue
}
variant := as2variant(as)
for i := range addvariant {
as2 := variant2as(as, variant|addvariant[i])
if as2 != 0 && progtable[as2&obj.AMask].Flags == 0 {
progtable[as2&obj.AMask] = progtable[as]
}
}
}
}
func archX86(linkArch *obj.LinkArch) *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
for i, s := range x86.Register {
register[s] = int16(i + x86.REG_AL)
}
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
// Register prefix not used on this architecture.
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range x86.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABaseAMD64
}
}
// Annoying aliases.
instructions["JA"] = x86.AJHI /* alternate */
instructions["JAE"] = x86.AJCC /* alternate */
instructions["JB"] = x86.AJCS /* alternate */
instructions["JBE"] = x86.AJLS /* alternate */
instructions["JC"] = x86.AJCS /* alternate */
instructions["JCC"] = x86.AJCC /* carry clear (CF = 0) */
instructions["JCS"] = x86.AJCS /* carry set (CF = 1) */
instructions["JE"] = x86.AJEQ /* alternate */
instructions["JEQ"] = x86.AJEQ /* equal (ZF = 1) */
instructions["JG"] = x86.AJGT /* alternate */
instructions["JGE"] = x86.AJGE /* greater than or equal (signed) (SF = OF) */
instructions["JGT"] = x86.AJGT /* greater than (signed) (ZF = 0 && SF = OF) */
instructions["JHI"] = x86.AJHI /* higher (unsigned) (CF = 0 && ZF = 0) */
instructions["JHS"] = x86.AJCC /* alternate */
instructions["JL"] = x86.AJLT /* alternate */
instructions["JLE"] = x86.AJLE /* less than or equal (signed) (ZF = 1 || SF != OF) */
instructions["JLO"] = x86.AJCS /* alternate */
instructions["JLS"] = x86.AJLS /* lower or same (unsigned) (CF = 1 || ZF = 1) */
instructions["JLT"] = x86.AJLT /* less than (signed) (SF != OF) */
instructions["JMI"] = x86.AJMI /* negative (minus) (SF = 1) */
instructions["JNA"] = x86.AJLS /* alternate */
instructions["JNAE"] = x86.AJCS /* alternate */
instructions["JNB"] = x86.AJCC /* alternate */
instructions["JNBE"] = x86.AJHI /* alternate */
instructions["JNC"] = x86.AJCC /* alternate */
instructions["JNE"] = x86.AJNE /* not equal (ZF = 0) */
instructions["JNG"] = x86.AJLE /* alternate */
instructions["JNGE"] = x86.AJLT /* alternate */
instructions["JNL"] = x86.AJGE /* alternate */
instructions["JNLE"] = x86.AJGT /* alternate */
instructions["JNO"] = x86.AJOC /* alternate */
instructions["JNP"] = x86.AJPC /* alternate */
instructions["JNS"] = x86.AJPL /* alternate */
instructions["JNZ"] = x86.AJNE /* alternate */
instructions["JO"] = x86.AJOS /* alternate */
instructions["JOC"] = x86.AJOC /* overflow clear (OF = 0) */
instructions["JOS"] = x86.AJOS /* overflow set (OF = 1) */
instructions["JP"] = x86.AJPS /* alternate */
instructions["JPC"] = x86.AJPC /* parity clear (PF = 0) */
instructions["JPE"] = x86.AJPS /* alternate */
instructions["JPL"] = x86.AJPL /* non-negative (plus) (SF = 0) */
instructions["JPO"] = x86.AJPC /* alternate */
instructions["JPS"] = x86.AJPS /* parity set (PF = 1) */
instructions["JS"] = x86.AJMI /* alternate */
instructions["JZ"] = x86.AJEQ /* alternate */
instructions["MASKMOVDQU"] = x86.AMASKMOVOU
instructions["MOVD"] = x86.AMOVQ
instructions["MOVDQ2Q"] = x86.AMOVQ
instructions["MOVNTDQ"] = x86.AMOVNTO
instructions["MOVOA"] = x86.AMOVO
instructions["PSLLDQ"] = x86.APSLLO
instructions["PSRLDQ"] = x86.APSRLO
instructions["PADDD"] = x86.APADDL
return &Arch{
LinkArch: linkArch,
Instructions: instructions,
Register: register,
RegisterPrefix: nil,
RegisterNumber: nilRegisterNumber,
IsJump: jumpX86,
}
}
func archArm64() *Arch {
register := make(map[string]int16)
// Create maps for easy lookup of instruction names etc.
// Note that there is no list of names as there is for 386 and amd64.
register[arm64.Rconv(arm64.REGSP)] = int16(arm64.REGSP)
for i := arm64.REG_R0; i <= arm64.REG_R31; i++ {
register[arm64.Rconv(i)] = int16(i)
}
for i := arm64.REG_F0; i <= arm64.REG_F31; i++ {
register[arm64.Rconv(i)] = int16(i)
}
for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {
register[arm64.Rconv(i)] = int16(i)
}
register["LR"] = arm64.REGLINK
register["DAIF"] = arm64.REG_DAIF
register["NZCV"] = arm64.REG_NZCV
register["FPSR"] = arm64.REG_FPSR
register["FPCR"] = arm64.REG_FPCR
register["SPSR_EL1"] = arm64.REG_SPSR_EL1
register["ELR_EL1"] = arm64.REG_ELR_EL1
register["SPSR_EL2"] = arm64.REG_SPSR_EL2
register["ELR_EL2"] = arm64.REG_ELR_EL2
register["CurrentEL"] = arm64.REG_CurrentEL
register["SP_EL0"] = arm64.REG_SP_EL0
register["SPSel"] = arm64.REG_SPSel
register["DAIFSet"] = arm64.REG_DAIFSet
register["DAIFClr"] = arm64.REG_DAIFClr
// Conditional operators, like EQ, NE, etc.
register["EQ"] = arm64.COND_EQ
register["NE"] = arm64.COND_NE
register["HS"] = arm64.COND_HS
register["CS"] = arm64.COND_HS
register["LO"] = arm64.COND_LO
register["CC"] = arm64.COND_LO
register["MI"] = arm64.COND_MI
register["PL"] = arm64.COND_PL
register["VS"] = arm64.COND_VS
register["VC"] = arm64.COND_VC
register["HI"] = arm64.COND_HI
register["LS"] = arm64.COND_LS
register["GE"] = arm64.COND_GE
register["LT"] = arm64.COND_LT
register["GT"] = arm64.COND_GT
register["LE"] = arm64.COND_LE
register["AL"] = arm64.COND_AL
register["NV"] = arm64.COND_NV
// Pseudo-registers.
register["SB"] = RSB
register["FP"] = RFP
register["PC"] = RPC
register["SP"] = RSP
// Avoid unintentionally clobbering g using R28.
delete(register, "R28")
register["g"] = arm64.REG_R28
registerPrefix := map[string]bool{
"F": true,
"R": true,
"V": true,
}
instructions := make(map[string]obj.As)
for i, s := range obj.Anames {
instructions[s] = obj.As(i)
}
for i, s := range arm64.Anames {
if obj.As(i) >= obj.A_ARCHSPECIFIC {
instructions[s] = obj.As(i) + obj.ABaseARM64
}
}
// Annoying aliases.
instructions["B"] = arm64.AB
instructions["BL"] = arm64.ABL
return &Arch{
LinkArch: &arm64.Linkarm64,
Instructions: instructions,
Register: register,
RegisterPrefix: registerPrefix,
RegisterNumber: arm64RegisterNumber,
IsJump: jumpArm64,
}
}
func initvariants() {
initvariant(ppc64.AADD, ppc64.AADDCC, ppc64.AADDV, ppc64.AADDVCC)
initvariant(ppc64.AADDC, ppc64.AADDCCC, ppc64.AADDCV, ppc64.AADDCVCC)
initvariant(ppc64.AADDE, ppc64.AADDECC, ppc64.AADDEV, ppc64.AADDEVCC)
initvariant(ppc64.AADDME, ppc64.AADDMECC, ppc64.AADDMEV, ppc64.AADDMEVCC)
initvariant(ppc64.AADDZE, ppc64.AADDZECC, ppc64.AADDZEV, ppc64.AADDZEVCC)
initvariant(ppc64.AAND, ppc64.AANDCC)
initvariant(ppc64.AANDN, ppc64.AANDNCC)
initvariant(ppc64.ACNTLZD, ppc64.ACNTLZDCC)
initvariant(ppc64.ACNTLZW, ppc64.ACNTLZWCC)
initvariant(ppc64.ADIVD, ppc64.ADIVDCC, ppc64.ADIVDV, ppc64.ADIVDVCC)
initvariant(ppc64.ADIVDU, ppc64.ADIVDUCC, ppc64.ADIVDUV, ppc64.ADIVDUVCC)
initvariant(ppc64.ADIVW, ppc64.ADIVWCC, ppc64.ADIVWV, ppc64.ADIVWVCC)
initvariant(ppc64.ADIVWU, ppc64.ADIVWUCC, ppc64.ADIVWUV, ppc64.ADIVWUVCC)
initvariant(ppc64.AEQV, ppc64.AEQVCC)
initvariant(ppc64.AEXTSB, ppc64.AEXTSBCC)
initvariant(ppc64.AEXTSH, ppc64.AEXTSHCC)
initvariant(ppc64.AEXTSW, ppc64.AEXTSWCC)
initvariant(ppc64.AFABS, ppc64.AFABSCC)
initvariant(ppc64.AFADD, ppc64.AFADDCC)
initvariant(ppc64.AFADDS, ppc64.AFADDSCC)
initvariant(ppc64.AFCFID, ppc64.AFCFIDCC)
initvariant(ppc64.AFCFIDU, ppc64.AFCFIDUCC)
initvariant(ppc64.AFCTID, ppc64.AFCTIDCC)
initvariant(ppc64.AFCTIDZ, ppc64.AFCTIDZCC)
initvariant(ppc64.AFCTIW, ppc64.AFCTIWCC)
initvariant(ppc64.AFCTIWZ, ppc64.AFCTIWZCC)
initvariant(ppc64.AFDIV, ppc64.AFDIVCC)
initvariant(ppc64.AFDIVS, ppc64.AFDIVSCC)
initvariant(ppc64.AFMADD, ppc64.AFMADDCC)
initvariant(ppc64.AFMADDS, ppc64.AFMADDSCC)
initvariant(ppc64.AFMOVD, ppc64.AFMOVDCC)
initvariant(ppc64.AFMSUB, ppc64.AFMSUBCC)
initvariant(ppc64.AFMSUBS, ppc64.AFMSUBSCC)
initvariant(ppc64.AFMUL, ppc64.AFMULCC)
initvariant(ppc64.AFMULS, ppc64.AFMULSCC)
initvariant(ppc64.AFNABS, ppc64.AFNABSCC)
initvariant(ppc64.AFNEG, ppc64.AFNEGCC)
initvariant(ppc64.AFNMADD, ppc64.AFNMADDCC)
initvariant(ppc64.AFNMADDS, ppc64.AFNMADDSCC)
initvariant(ppc64.AFNMSUB, ppc64.AFNMSUBCC)
initvariant(ppc64.AFNMSUBS, ppc64.AFNMSUBSCC)
initvariant(ppc64.AFRES, ppc64.AFRESCC)
initvariant(ppc64.AFRSP, ppc64.AFRSPCC)
initvariant(ppc64.AFRSQRTE, ppc64.AFRSQRTECC)
initvariant(ppc64.AFSEL, ppc64.AFSELCC)
initvariant(ppc64.AFSQRT, ppc64.AFSQRTCC)
initvariant(ppc64.AFSQRTS, ppc64.AFSQRTSCC)
initvariant(ppc64.AFSUB, ppc64.AFSUBCC)
initvariant(ppc64.AFSUBS, ppc64.AFSUBSCC)
initvariant(ppc64.AMTFSB0, ppc64.AMTFSB0CC)
initvariant(ppc64.AMTFSB1, ppc64.AMTFSB1CC)
initvariant(ppc64.AMULHD, ppc64.AMULHDCC)
initvariant(ppc64.AMULHDU, ppc64.AMULHDUCC)
initvariant(ppc64.AMULHW, ppc64.AMULHWCC)
initvariant(ppc64.AMULHWU, ppc64.AMULHWUCC)
initvariant(ppc64.AMULLD, ppc64.AMULLDCC, ppc64.AMULLDV, ppc64.AMULLDVCC)
initvariant(ppc64.AMULLW, ppc64.AMULLWCC, ppc64.AMULLWV, ppc64.AMULLWVCC)
initvariant(ppc64.ANAND, ppc64.ANANDCC)
initvariant(ppc64.ANEG, ppc64.ANEGCC, ppc64.ANEGV, ppc64.ANEGVCC)
initvariant(ppc64.ANOR, ppc64.ANORCC)
initvariant(ppc64.AOR, ppc64.AORCC)
initvariant(ppc64.AORN, ppc64.AORNCC)
initvariant(ppc64.AREM, ppc64.AREMCC, ppc64.AREMV, ppc64.AREMVCC)
initvariant(ppc64.AREMD, ppc64.AREMDCC, ppc64.AREMDV, ppc64.AREMDVCC)
initvariant(ppc64.AREMDU, ppc64.AREMDUCC, ppc64.AREMDUV, ppc64.AREMDUVCC)
initvariant(ppc64.AREMU, ppc64.AREMUCC, ppc64.AREMUV, ppc64.AREMUVCC)
initvariant(ppc64.ARLDC, ppc64.ARLDCCC)
initvariant(ppc64.ARLDCL, ppc64.ARLDCLCC)
initvariant(ppc64.ARLDCR, ppc64.ARLDCRCC)
initvariant(ppc64.ARLDMI, ppc64.ARLDMICC)
initvariant(ppc64.ARLWMI, ppc64.ARLWMICC)
initvariant(ppc64.ARLWNM, ppc64.ARLWNMCC)
initvariant(ppc64.ASLD, ppc64.ASLDCC)
initvariant(ppc64.ASLW, ppc64.ASLWCC)
initvariant(ppc64.ASRAD, ppc64.ASRADCC)
initvariant(ppc64.ASRAW, ppc64.ASRAWCC)
initvariant(ppc64.ASRD, ppc64.ASRDCC)
initvariant(ppc64.ASRW, ppc64.ASRWCC)
initvariant(ppc64.ASUB, ppc64.ASUBCC, ppc64.ASUBV, ppc64.ASUBVCC)
initvariant(ppc64.ASUBC, ppc64.ASUBCCC, ppc64.ASUBCV, ppc64.ASUBCVCC)
initvariant(ppc64.ASUBE, ppc64.ASUBECC, ppc64.ASUBEV, ppc64.ASUBEVCC)
initvariant(ppc64.ASUBME, ppc64.ASUBMECC, ppc64.ASUBMEV, ppc64.ASUBMEVCC)
initvariant(ppc64.ASUBZE, ppc64.ASUBZECC, ppc64.ASUBZEV, ppc64.ASUBZEVCC)
initvariant(ppc64.AXOR, ppc64.AXORCC)
for i := range varianttable {
vv := &varianttable[i]
if vv[0] == 0 {
// Instruction has no variants
varianttable[i][0] = obj.As(i)
continue
}
// Copy base form to other variants
if vv[0]&obj.AMask == obj.As(i) {
for _, v := range vv {
if v != 0 {
varianttable[v&obj.AMask] = varianttable[i]
}
}
}
}
}